1. Field of the Invention
The present invention relates to a package substrate and a manufacture method thereof, particularly to a thin double-sided package substrate and a manufacture method thereof
2. Description of the Related Art
Refer to FIG. 1. In a conventional package substrate having circuits on both sides thereof, conductive layers 12 and 13 are respectively formed on the upper and lower surfaces of a carrier 11, and the desired circuits are formed on the conductive layers 12 and 13. A through-hole 14 penetrates the carrier 11, and a conductive element 15 is set inside the through-hole 14 to electrically connect the conductive layer 12 with the conductive layer 13. Besides, an insulating material, such as a resin or a solder mask, may further be filled into the through-hole 14. A metal finishing process is used to form a solder pad 17. A solder mask layer 16 is formed on the conductive layers 12 and 13 with the solder pad 17 exposed.
As shown in FIG. 1, a chip 21 is fixedly installed on the package substrate, and wires 22 electrically connect the chip 21 with package substrate. Then, an encapsulant 23 is used to encapsulate the chip 21, the wires 22, etc., to complete the package of a chip. However, the abovementioned package structure has the following disadvantages: 1. The solder mask layer 16, the conductive layers 12 and 13, and carrier 11 are likely to peel off because of the poor bonding therebetween; 2. Humidity is likely to permeate from the non-encapsulated lower surface of the carrier 11 through the inner wall of the through-hole 14 to the upper surface of the carrier 11 because the through-hole 14 penetrates the carrier 11 and the conductive layers 12 and 13, and the reliability of the circuit is thus reduced. Besides, the chip 21 is fixedly installed on the package substrate which not only makes worse the heat dissipation of the chip 21 but also impairs the slimming of the chip package.
Therefore, how to promote reliability, reduce thickness, enhance heat dissipation and increase layout flexibility in a chip package has become an important topic in the fields concerned.